The Best of ICCAD: 20 Years of Excellence in Computer-Aided Design
In 2002, the International Conference on Computer Aided Design (ICCAD) celebrates its 20th anniversary. This book commemorates contributions made by ICCAD to the broad field of design automation during that time. The foundation of ICCAD in 1982 coincided with the growth of Large Scale Integration. The sharply increased functionality of board-level circuits led to a major demand for more powerful Electronic Design Automation (EDA) tools. At the same time, LSI grew quickly and advanced circuit integration became widely avail able. This, in turn, required new tools, using sophisticated modeling, analysis and optimization algorithms in order to manage the evermore complex design processes. Not surprisingly, during the same period, a number of start-up com panies began to commercialize EDA solutions, complementing various existing in-house efforts. The overall increased interest in Design Automation (DA) re quired a new forum for the emerging community of EDA professionals; one which would be focused on the publication of high-quality research results and provide a structure for the exchange of ideas on a broad scale. Many of the original ICCAD volunteers were also members of CANDE (Computer-Aided Network Design), a workshop of the IEEE Circuits and Sys tem Society. In fact, it was at a CANDE workshop that Bill McCalla suggested the creation of a conference for the EDA professional. (Bill later developed the name).
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algorithm analog analog circuit analysis AND2/INV applied approach assignment BDDs benchmark Binary Decision Diagrams Boolean functions boolean network Brayton capacitance chip circuit simulator clock period cluster CMOS complex Computer Aided Design Computer-Aided Design constraints cost cycle datapath decomposition delay Design Automation Conference device divisors edges efficient equations equivalent example faults Figure ﬁrst floorplan FPGA gate global heuristic ICCAD IEEE IEEE Trans IEEE Transactions implementation input Integrated Circuits interconnect International Conference iteration latch latency layout Lemma linear logic synthesis mapping graph matrix method min-cut minimization minimum module node noise sources nonlinear OBDD operations optimization output paper parameters partitioning path performance placement problem Proc procedure reduced retiming Sangiovanni-Vincentelli schedule signal simulated annealing solution solve techniques technology mapping testable Theorem tion transformations transistor tree vector verification VLSI voltage