Asynchronous CircuitsSpringer Science & Business Media, 6 בדצמ׳ 2012 - 404 עמודים Although asynchronous circuits date back to the early 1950s most of the digital circuits in use today are synchronous because, traditionally, asynchronous circuits have been viewed as difficult to understand and design. In recent years, however, there has been a great surge of interest in asynchronous circuits, largely through the development of new asynchronous design methodologies. This book provides a comprehensive theory of asynchronous circuits, including modelling, analysis, simulation, specification, verification, and an introduction to their design. It is based on courses given to graduate students and will be suitable for computer scientists and engineers involved in the research and development of asynchronous designs. |
תוכן
| 1 | |
1 | 22 |
Delay Models | 35 |
Gate Circuits | 47 |
CMOS Transistor Circuits | 61 |
4 | 71 |
7 | 79 |
Contents | 88 |
3 | 192 |
5 | 204 |
1 | 214 |
6 | 229 |
7 | 235 |
Types of Behaviors | 241 |
1 | 256 |
5 | 270 |
Stable States and FeedbackState Networks | 97 |
UpBounded Ideal Delays | 103 |
Ternary Simulation | 117 |
BiBounded Delay Models | 143 |
1 | 162 |
1 | 186 |
Contents | 280 |
Design of Asynchronous Circuits 313 | 312 |
| 367 | |
List of Figures | 379 |
List of Tables | 385 |
מהדורות אחרות - הצג הכל
Asynchronous Circuits <span dir=ltr>Janusz A. Brzozowski</span>,<span dir=ltr>Carl-Johan H. Seger</span> תצוגה מקדימה מוגבלת - 1995 |
Asynchronous Circuits <span dir=ltr>Janusz A. Brzozowski</span>,<span dir=ltr>Carl-Johan H. Seger</span> אין תצוגה מקדימה זמינה - 2011 |
Asynchronous Circuits <span dir=ltr>Janusz A. Brzozowski</span>,<span dir=ltr>Carl-Johan H. Seger</span> אין תצוגה מקדימה זמינה - 2011 |
מונחים וביטויים נפוצים
Algorithm assume assumption asynchronous circuits automaton bi-bounded delay binary relation binary value Boolean functions bounded C-ELEMENT cell Chapter circuit graph circuit of Figure clock CMOS CMOS circuit components compute consider construction corresponding cycle defined delay model delay-insensitive denote edge example excitation functions feedback vertex set flow table follows fundamental-mode gate circuit gate vertex GMW analysis hazards Hence I-nets illustrate induction inertial delay input changes input-delay input/output inverter labeled language latch Lemma livelock logic model checking modules Moore machine n-tuple nontransient NP-hard O₁ OBDD operation oscillation out(Ra(b outcome output path Proof properties Proposition q₁ quotient race model reachable realization regular expression regular languages relation s₁ Section sequence sh+1 shown in Figure signal specification stable total static symbolic TBD algorithm ternary simulation Theorem transistor transition vector verify vertex function vertices waveform wire vertex word X₁ y₁