Asynchronous CircuitsSpringer Science & Business Media, 24 בפבר׳ 1995 - 404 עמודים Although asynchronous circuits date back to the early 1950s most of the digital circuits in use today are synchronous because, traditionally, asynchronous circuits have been viewed as difficult to understand and design. In recent years, however, there has been a great surge of interest in asynchronous circuits, largely through the development of new asynchronous design methodologies. This book provides a comprehensive theory of asynchronous circuits, including modelling, analysis, simulation, specification, verification, and an introduction to their design. It is based on courses given to graduate students and will be suitable for computer scientists and engineers involved in the research and development of asynchronous designs. |
תוכן
Introductory Examples | 1 |
11 Logic Gates | 2 |
12 Performance Estimation | 3 |
13 RS FlipFlop | 8 |
14 Dynamic CMOS Logic | 10 |
15 Divideby2 Counter | 16 |
16 Summary | 21 |
Mathematical Background | 23 |
105 Equivalence and Reduction of Automata | 205 |
106 Nondeterministic Automata | 207 |
107 Expression Automata | 209 |
Behaviors and Realizations | 213 |
111 Motivation | 214 |
112 Behaviors | 215 |
113 Projections of Implementations to Specifications | 220 |
114 Relevant Words | 223 |
22 Boolean Algebra | 25 |
23 Ternary Algebra | 28 |
24 Directed Graphs | 32 |
Delay Models | 35 |
32 Gates with Delays | 36 |
33 Ideal Delays | 38 |
34 Inertial Delays | 40 |
Gate Circuits | 45 |
42 Classes of Gate Circuits | 47 |
43 The Circuit Graph | 50 |
44 Network Models | 53 |
45 Models of More Complex Gates | 57 |
CMOS Transistor Circuits | 61 |
52 Combinational CMOS Circuits | 67 |
53 General CMOS Circuits | 69 |
54 Node Excitation Functions | 71 |
55 Path Strength Models | 73 |
56 Capacitance Effects | 75 |
57 Network Model of CMOS Circuits | 79 |
UpBoundedDelay Race Models | 83 |
61 The General MultipleWinner Model | 84 |
62 GMW Analysis and UIN Delays | 92 |
63 The Outcome in GMW Analysis | 95 |
64 Stable States and FeedbackState Networks | 97 |
65 GMW Analysis and Network Models | 99 |
66 The Extended GMW Model | 101 |
67 SingleWinner Race Models | 102 |
68 UpBounded Ideal Delays | 103 |
69 Proofs | 107 |
692 Proofs for Section 63 | 110 |
Ternary Simulation | 113 |
72 Algorithm A | 118 |
73 Algorithm B | 121 |
74 FeedbackDelay Models | 123 |
75 Hazards | 127 |
752 Dynamic Hazards | 129 |
77 Ternary Simulation and the XMW Model | 131 |
78 Proofs of Main Results | 132 |
BiBounded Delay Models | 143 |
81 Discrete Binary Models | 144 |
82 Continuous Binary Model | 148 |
83 Algorithms for Continuous Binary Analysis | 152 |
84 Continuous Ternary Model | 156 |
85 Discrete Ternary Model | 162 |
Complexity of Race Analysis | 167 |
92 Limited Reachability | 181 |
Regular Languages and Finite Automata | 187 |
1012 Languages | 188 |
1013 Regular Languages | 189 |
1014 Quotients of Languages | 190 |
102 Regular Expressions | 192 |
1022 Quotients of Regular Expressions | 193 |
103 Quotient Equations | 198 |
104 Finite Automata | 202 |
1042 Recognizable Languages | 204 |
1142 Different Input and Output Alphabets | 224 |
115 Proper Behaviors | 225 |
116 Realization | 229 |
1162 Deadlock | 230 |
1163 Livelock | 232 |
1164 Definition of Realization | 234 |
117 Behavior Schemas | 235 |
118 Concluding Remarks | 240 |
Types of Behaviors | 241 |
122 FundamentalMode Specifications | 244 |
123 FundamentalMode Network Behaviors | 246 |
124 Direct Behaviors | 249 |
125 Serial Behaviors | 251 |
Limitations of UpBounded Delay Models | 255 |
131 DelayInsensitivity in Fundamental Mode | 256 |
132 Composite Functions | 258 |
133 Main Theorem for Fundamental Mode | 259 |
134 DelayInsensitivity in InputOutput Mode | 263 |
1342 Some Behaviors Without DI Realizations | 269 |
1343 Nontrivial Sequential Behaviors | 270 |
135 Concluding Remarks | 272 |
Symbolic Analysis | 275 |
141 Representing Boolean Functions | 276 |
142 Symbolic Representations | 279 |
1422 Sets | 280 |
1423 Relations | 281 |
1424 Behaviors | 283 |
143 Deriving Symbolic Behaviors | 284 |
144 Symbolic Race Analysis | 288 |
1441 Symbolic Ternary Simulation | 289 |
1442 Symbolic BoundedDelay Analysis | 290 |
145 Symbolic Verification of Realization | 297 |
146 Symbolic Model Checking | 303 |
Design of Asynchronous Circuits | 313 |
152 FundamentalMode Huffman Circuits | 318 |
153 Hollaar Circuits | 320 |
154 BurstMode Circuits | 321 |
155 Module Synthesis Using INets | 325 |
156 Signal Transition Graphs | 331 |
157 Change Diagrams | 339 |
158 Protocols in DI Circuits | 341 |
159 Ebergens Trace Theory Method | 343 |
1510 Compilation of Communicating Processes | 348 |
1511 Handshake Circuits | 357 |
1512 ModuleBased Compilation Systems | 360 |
1513 DCVSL and Interconnection Modules | 361 |
1514 Micropipelines | 363 |
1515 Concluding Remarks | 366 |
Bibliography | 367 |
List of Figures | 379 |
| 385 | |
| 387 | |
| 391 | |
מהדורות אחרות - הצג הכל
Asynchronous Circuits <span dir=ltr>Janusz A. Brzozowski</span>,<span dir=ltr>Carl-Johan H. Seger</span> תצוגה מקדימה מוגבלת - 2012 |
Asynchronous Circuits <span dir=ltr>Janusz A. Brzozowski</span>,<span dir=ltr>Carl-Johan H. Seger</span> אין תצוגה מקדימה זמינה - 2011 |
Asynchronous Circuits <span dir=ltr>Janusz A. Brzozowski</span>,<span dir=ltr>Carl-Johan H. Seger</span> אין תצוגה מקדימה זמינה - 2011 |
מונחים וביטויים נפוצים
Algorithm assume assumption asynchronous circuits automaton bi-bounded delay binary relation binary value Boolean functions bounded C-ELEMENT cell Chapter circuit graph circuit of Figure clock CMOS CMOS circuit components compute consider construction corresponding cycle defined delay model delay-insensitive denote edge example excitation functions extended regular expression feedback vertex set flow table follows fundamental-mode gate circuit gate vertex GMW analysis hazards Hence I-nets illustrate induction inertial delay input changes input-delay input/output inverter labeled latch Lemma livelock logic model checking modules Moore machine n-tuple nontransient NP-hard OBDD operation oscillation outcome output path Proof properties q₁ quotient race model reachable realization regular expression regular languages relation result of Algorithm s₁ Section sequence sh+1 shown in Figure signal specification stable total static symbolic ternary simulation th+1 Theorem transistor transition vector verify vertex function vertices waveform wire vertex word X₁ Y₁
קטעים בולטים
עמוד 369 - T.-A. Chu. Synthesis of Self-timed VLSI Circuits from Graphtheoretic Specifications.
עמוד 371 - LG Heller, WR Griffin, JW Davis, and NG Thoma. Cascode voltage switch logic: A differential CMOS logic family.
עמוד 369 - Computing Signal Delay in General RC Networks by Tree/Link Partitioning", IEEE Transactions on Computer-Aided Design, vol.
עמוד 370 - Coudert, JC Madre, and C. Berthet. Verifying temporal properties of sequential machines without building their state diagrams.
עמוד 370 - The Post Office experience: Designing a large asynchronous chip," Integration, the VLSI journal, vol.