Principles of Asynchronous Circuit Design: A Systems PerspectiveJens Sparsø, Steve Furber Springer Science & Business Media, 17 באפר׳ 2013 - 337 עמודים Principles of Asynchronous Circuit Design - A Systems Perspective addresses the need for an introductory text on asynchronous circuit design. Part I is an 8-chapter tutorial which addresses the most important issues for the beginner, including how to think about asynchronous systems. Part II is a 4-chapter introduction to Balsa, a freely-available synthesis system for asynchronous circuits which will enable the reader to get hands-on experience of designing high-level asynchronous systems. Part III offers a number of examples of state-of-the-art asynchronous systems to illustrate what can be built using asynchronous techniques. The examples range from a complete commercial smart card chip to complex microprocessors. The objective in writing this book has been to enable industrial designers with a background in conventional (clocked) design to be able to understand asynchronous design sufficiently to assess what it has to offer and whether it might be advantageous in their next design task. |
תוכן
| 2 | |
Fundamentals | 9 |
2 | 15 |
5 | 23 |
3 | 29 |
4 | 33 |
4 | 41 |
5 | 56 |
6 | 81 |
7 | 115 |
8 | 123 |
Balsa An Asynchronous Hardware Synthesis System | 153 |
The Balsa language | 173 |
LargeScale Asynchronous Designs | 221 |
14 | 249 |
Processors | 273 |
מהדורות אחרות - הצג הכל
Principles of Asynchronous Circuit Design <span dir=ltr>Jens Sparso</span>,<span dir=ltr>Steve Furber</span> אין תצוגה מקדימה זמינה - 2014 |
מונחים וביטויים נפוצים
4-phase bundled-data 4-phase dual-rail acknowledge signal adder Amulet3 arbiter array Asynchronous Circuit Design asynchronous circuits asynchronous design asynchronous system backtrace Balsa behaviour bits Boolean bubble byte C-element cache chan channel_fp chapter chronous clock codeword compilation Computer contactless control circuits count count_reg cycle decoder delay delay-insensitive DMA controller empty token encoded end end environment error example fetch fork full adder function blocks gates global winner graph handshake circuit handshake components illustrated implementation indicating indicating function initial input channel input signals instruction interface Karnaugh map latch controller latency logic loop low-power memory microcontroller microprocessor Mifare MUTEX node operation output channel parameter performance Petri net Petrify pipeline pipeline stages port prefetch procedure processor reorder buffer request reset result ripple-carry adder sequence sequential shown in figure signal transitions simulation slot specification speed-independent Tangram timeslot variable VHDL VLSI wires