Principles of Asynchronous Circuit Design: A Systems PerspectiveJens Sparsø, Stephen Bo Furber Springer Science & Business Media, 31 בדצמ׳ 2001 - 337 עמודים Principles of Asynchronous Circuit Design - A Systems Perspective addresses the need for an introductory text on asynchronous circuit design. Part I is an 8-chapter tutorial which addresses the most important issues for the beginner, including how to think about asynchronous systems. Part II is a 4-chapter introduction to Balsa, a freely-available synthesis system for asynchronous circuits which will enable the reader to get hands-on experience of designing high-level asynchronous systems. Part III offers a number of examples of state-of-the-art asynchronous systems to illustrate what can be built using asynchronous techniques. The examples range from a complete commercial smart card chip to complex microprocessors. The objective in writing this book has been to enable industrial designers with a background in conventional (clocked) design to be able to understand asynchronous design sufficiently to assess what it has to offer and whether it might be advantageous in their next design task. |
תוכן
Chapter 1 INTRODUCTION | 3 |
12 Aims and background | 4 |
13 Clocking versus handshaking | 5 |
14 Outline of Part I | 8 |
Chapter 2 FUNDAMENTALS | 9 |
212 The 4phase dualrail protocol | 11 |
213 The 2phase dualrail protocol | 13 |
22 The Muller Celement and the indication principle | 14 |
863 Channel communication and design flow | 136 |
864 The abstract channel package | 138 |
865 The real channel package | 142 |
866 Partitioning into control and data | 144 |
87 Summary | 146 |
The VIIDL channel packages | 148 |
A2 The real channel package | 150 |
AN INTRODUCTION TO BALSA | 155 |
23 The Muller pipeline | 16 |
24 Circuit implementation styles | 17 |
241 4phase bundleddata | 18 |
242 2phase bundled data Micropipelines | 19 |
243 4phase dualrail | 20 |
25 Theory | 23 |
252 Classification of asynchronous circuits | 25 |
253 Isochronic forks | 26 |
26 Test | 27 |
27 Summary | 28 |
STATIC DATAFLOW STRUCTURES | 29 |
32 Pipelines and rings | 30 |
33 Building blocks | 31 |
34 A simple example | 33 |
35 Simple applications of rings | 35 |
36 FOR IF and WHILE constructs | 36 |
GCD | 38 |
38 Pointers to additional examples | 39 |
383 A finegrain pipelined vector multiplier | 40 |
Chapter 4 PERFORMANCE | 41 |
42 A qualitative view of performance | 42 |
A shift register with parallel load | 44 |
43 Quantifying performance | 47 |
432 Cycle time of a ring | 49 |
Performance of a 3stage ring | 51 |
434 Final remarks | 52 |
Dependency graph for a 3stage ring | 54 |
45 Summary | 56 |
HANDSHAKE CIRCUIT IMPLEMENTATIONS | 57 |
52 Fork join and merge | 58 |
53 Function blocks The basics | 60 |
532 Transparency to handshaking | 61 |
533 Review of ripplecarry addition | 64 |
54 Bundleddata function blocks | 65 |
542 Delay selection | 66 |
55 Dualrail function blocks | 67 |
552 Null Convention Logic | 69 |
553 Transistorlevel CMOS implementations | 70 |
554 Martins adder | 71 |
56 Hybrid function blocks | 73 |
57 MUX and DEMUX | 75 |
58 Mutual exclusion arbitration and metastability | 77 |
582 Arbitration | 79 |
59 Summary | 80 |
SPEEDINDEPENDENT CONTROL CIRCUITS | 81 |
612 Hazards | 82 |
613 Delay models | 83 |
615 Synthesis of fundamental mode circuits | 84 |
62 Signal transition graphs | 86 |
622 Some frequently used STG fragments | 88 |
63 The basic synthesis procedure | 91 |
a Celement | 92 |
Hazards in the simple gate implementation | 94 |
64 Implementations using stateholding gates | 96 |
642 Excitation regions and quiescent regions | 97 |
Using stateholding elements | 98 |
645 Circuit topologies using stateholding elements | 99 |
65 Initialization | 101 |
A tool for synthesizing SI circuits from STGs | 102 |
68 Design examples using Petrify | 104 |
682 Control circuit for a 4phase bundleddata latch | 106 |
683 Control circuit for a 4phase bundleddata MUX | 109 |
69 Summary | 113 |
ADVANCED 4PHASE BUNDLEDDATA PROTOCOLS AND CIRCUITS | 115 |
712 Datavalidity schemes | 116 |
72 Static type checking | 118 |
73 More advanced latch control circuits | 119 |
74 Summary | 121 |
HIGHLEVEL LANGUAGES AND TOOLS | 123 |
82 Concurrency and message passing in CSP | 124 |
program examples | 126 |
833 GCD using while and if statements | 127 |
834 GCD using guarded commands | 128 |
841 The 2place shift register | 129 |
842 The 2place FIFO | 130 |
843 GCD using guarded repetition | 131 |
85 Martins translation process | 133 |
86 Using VHDL for asynchronous design | 134 |
862 VHDL versus CSPtype languages | 135 |
92 Basic concepts | 156 |
93 Tool set and design flow | 159 |
941 A singleplace buffer | 161 |
942 Twoplace buffers 1st design | 163 |
943 Parallel composition and module reuse | 164 |
944 Placing multiple structures | 165 |
95 Ancillary Balsa tools | 166 |
952 Estimating area cost | 167 |
953 Viewing the handshake circuit graph | 168 |
THE BALSA LANGUAGE | 173 |
102 Data typing issues | 176 |
103 Control flow and commands | 178 |
104 Binaryunary operators | 181 |
106 Example circuits | 183 |
107 Selecting channels | 190 |
BUILDING LIBRARY COMPONENTS | 193 |
1112 Pipelines of variable width and depth | 194 |
112 Recursive definitions | 195 |
1122 A population counter | 197 |
1123 A Balsa shifter | 200 |
1124 An arbiter tree | 202 |
A SIMPLE DMA CONTROLLER | 205 |
122 Channel registers | 206 |
123 DMA controller structure | 207 |
124 The Balsa description | 211 |
1242 Transfer engine | 212 |
1243 Control unit | 213 |
DESCALE | 221 |
131 Introduction | 222 |
132 VLSI programming of asynchronous circuits | 223 |
1322 Handshake technology | 225 |
1323 GCD algorithm | 226 |
133 Opportunities for asynchronous circuits | 231 |
134 Contactless smartcards | 232 |
135 The digital circuit | 235 |
1351 The 80C51 microcontroller | 236 |
1352 The prefetch unit | 239 |
1353 The DES coprocessor | 241 |
136 Results | 243 |
137 Test | 245 |
138 The power supply unit | 246 |
139 Conclusions | 247 |
AN ASYNCHRONOUS VITERBI DECODER | 249 |
142 The Viterbi decoder | 250 |
1422 Decoder principle | 251 |
143 System parameters | 253 |
144 System overview | 254 |
145 The Path Metric Unit PMU | 256 |
1452 Branch metrics | 259 |
1453 Slot timing | 261 |
1454 Global winner identification | 262 |
146 The History Unit HU | 264 |
1463 History Unit implementation | 267 |
147 Results and design evaluation | 269 |
148 Conclusions | 271 |
1481 Acknowledgement | 272 |
Chapter 15 PROCESSORS | 273 |
151 An introduction to the Amulet processors | 274 |
1512 Amulet2e 1996 | 275 |
152 Some other asynchronous microprocessors | 276 |
153 Processors as design examples | 278 |
154 Processor implementation techniques | 279 |
1542 Asynchronous pipeline architectures | 281 |
1543 Determinism and nondeterminism | 282 |
1544 Dependencies | 288 |
1545 Exceptions | 297 |
155 Memory a case study | 302 |
1552 The Amulet3i RAM | 303 |
1553 Cache | 307 |
156 Larger asynchronous systems | 310 |
1563 Balsa and the DMA controller | 312 |
1564 Calibrated time delays | 313 |
1565 Production test | 314 |
157 Summary | 315 |
Epilogue | 317 |
| 319 | |
| 333 | |
מהדורות אחרות - הצג הכל
Principles of Asynchronous Circuit Design <span dir=ltr>Jens Sparso</span>,<span dir=ltr>Steve Furber</span> אין תצוגה מקדימה זמינה - 2014 |
מונחים וביטויים נפוצים
4-phase bundled-data 4-phase dual-rail acknowledge signal adder Amulet3 arbiter array Asynchronous Circuit Design asynchronous circuits asynchronous design asynchronous systems backtrace Balsa behaviour bits Boolean bubble byte C-element cache chan channel_fp chapter chronous clock codeword compilation computed contactless control circuits count count_reg cycle decoder delay delay-insensitive DMA controller empty token encoded end end environment error example fetch fork full adder function blocks gate global winner graph handshake circuit handshake components illustrated indicating indicating function initial input channel input signals instruction interface Karnaugh map latch controller latency logic loop low-power memory microcontroller microprocessor Mifare MUTEX node operation output channel parameter performance Petri net Petrify pipeline stages port prefetch procedure processor reorder buffer request reset result ripple-carry adder sequence sequential shown in figure signal transitions simulation slot specification speed-independent synthesis Tangram timeslot valid token variable VHDL Viterbi decoder wires
קטעים בולטים
עמוד 328 - In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems. IEEE Computer Society Press, Apr.
עמוד 321 - SM Burns and AJ Martin. Syntax-directed translation of concurrent programs into self-timed circuits. In Advanced Research in VLSI: Proceedings of the 5th MIT Conference, pages 35-50, 1988.
עמוד 330 - Asynchronous circuits for low power: A DCC error corrector. IEEE Design & Test of Computers, pages 22-32, Summer 1994.
עמוד 329 - In S. Furber and M. Edwards, editors, Asynchronous Design Methodologies, volume A-28 of IFIP Transactions, pages 165-179.
עמוד 321 - T.-A. Chu. Synthesis of Self-timed VLSI Circuits from Graphtheoretic Specifications.
עמוד 330 - Berkel. Handshake Circuits: an Asynchronous Architecture for VLSI Programming, volume 5 of International Series on Parallel Computation. Cambridge University Press, 1993.
עמוד 330 - CH van Berkel, R. Burgess, J. Kessels, A. Peelers, M. Roncken, and F. Schalij. Asynchronous circuits for low power: a DCC error corrector.
עמוד 326 - AJ Martin, SM Burns, TK Lee, D. Borkovic, and PJ Hazewindus. The design of an asynchronous microprocessor.