Field-Programmable Logic and Applications. From FPGAs to Computing Paradigm: 8th International Workshop, FPL'98 Tallinn, Estonia, August 31 - September 3, 1998 ProceedingsReiner Hartenstein, Andres Keevallik Springer Science & Business Media, 1998 - 533 עמודים This book constitutes the refereed proceedings of the 8th International Workshop on Field-Programmable Logics and Applications, FPL '98, held in Tallinn, Estonia, in August/September 1998. The 39 revised full papers presented were carefully selected for inclusion in the book from a total of 86 submissions. Also included are 30 refereed high-quality posters. The papers are organized in topical sections on design methods, general aspects, prototyping and simulation, development methods, accelerators, system architectures, hardware/software codesign, system development, algorithms on FPGAs, and applications. |
תוכן
Design flow for functional simulation | 4 |
A Language for Parametrised | 9 |
Integrated Development Environment for Logic Synthesis | 19 |
1 | 29 |
1 | 39 |
Catalyst for New | 49 |
RunTime Management of | 59 |
Acceleration of Satisfiability Algorithms by | 69 |
A Hardware Operating System for Dynamic | 431 |
High Speed Low Level Image Processing on FPGAs | 436 |
A Flexible Implementation of HighPerformance | 441 |
444 | 444 |
Implementing Processor Arrays on FPGAs | 446 |
Reconfigurable Hardware | 451 |
StatechartBased HWSWCodesign of a | 456 |
Preface | 467 |
An Optimized Design Flow | 79 |
A KnowledgeBased System for Prototyping on | 89 |
JVX A Rapid Prototyping System Based on | 99 |
Prototyping New ILP Architectures Using FPGAs | 109 |
CAD System for ASM and FSM Synthesis | 119 |
Fast Floorplanning for FPGAs | 129 |
Design Entry | 130 |
A Fault Model for the | 139 |
Reconfigurable Hardware as Shared Resource | 149 |
The Bridge between | 159 |
A Reconfigurable Engine for RealTime | 169 |
An FPGA Implementation of a Magnetic | 179 |
Exploiting Contemporary Memory Techniques in | 189 |
Self Modifying Circuitry | 199 |
Reactive Environment for Runtime | 209 |
Evaluation of the XC6200Series Architecture | 218 |
An FPGABased Object Recognition Machine | 228 |
Applying | 238 |
InstructionLevel Parallelism | 248 |
A HardwareSoftware Codesign Environment for | 258 |
Mapping Loops onto Reconfigurable Architectures | 268 |
Speed Optimization of the ALR Circuit | 278 |
Top Data Bus | 279 |
HighLevel Synthesis for Dynamically Reconfigurable | 288 |
Dynamic Specialisation of XC6200 FPGAs by Partial | 298 |
FDC | 300 |
A Circuit Debug Tool | 308 |
D | 311 |
Computing Goldbach Partitions | 316 |
F | 321 |
Solving Boolean Satisfiability with Dynamic | 326 |
Modular Exponent Realization on FPGAs | 336 |
Carry in | 341 |
Cost Effective 2x2 Inner Product Processors | 348 |
k | 350 |
Р | 351 |
A FieldProgrammable GateArray System for | 356 |
A Transmutable Telecom System | 366 |
Fig 3 A photograph of the buffer board | 371 |
A Survey of Reconfigurable Computing Architectures | 376 |
A Novel Field Programmable Gate Array Architecture | 386 |
Accelerating DTP with Reconfigurable Computing | 391 |
An Interactive Datasheet for the Xilinx XC6200 | 401 |
Fast Adaptive Image Processing in FPGAs | 406 |
Increasing Microprocessor Performance with | 411 |
A HighPerformance Computing Module for a Low | 416 |
A High Performance Interconnect | 421 |
18090 | 422 |
A Hardware Implementation of Constraint Satisfaction | 426 |
Organization | 469 |
Table of Contents | 469 |
Constraints Hurdles and Opportunities | 3 |
Architectural Design Space Exploration Achieved | 5 |
Power Models | 16 |
Power MacroModelling for FirmMacro | 26 |
RTL Estimation of Steering Logic Power | 38 |
Reducing Power Consumption | 49 |
Framework for HighLevel Power Estimation | 58 |
Adaptive Bus Encoding Technique | 68 |
Accurate Power Estimation of Logic Structures | 78 |
2 | 83 |
A Holistic Approach | 88 |
Early Power Estimation | 108 |
DesignSpace Exploration of Low Power Coarse Grained | 118 |
Internal Power Dissipation Modeling and Minimization | 129 |
Impact of Voltage Scaling | 139 |
Degradation Delay Model Extension | 149 |
Second Generation Delay Model | 163 |
Semimodular Latch Chains | 168 |
Asynchronous Firstin Firstout Queues | 178 |
handshake | 180 |
Comparative Study on SelfChecking CarryPropagate | 187 |
VLSI Implementation of a LowPower HighSpeed | 195 |
Low Power Design Techniques | 205 |
Dynamic Memory Design | 207 |
Data | 210 |
DoubleLatch Clocking Scheme | 217 |
The condition on the clocks ensures that there is no | 223 |
Architecture Design and Verification | 225 |
CostEfficient CLevel Design | 233 |
DataReuse and Parallel Embedded | 243 |
Design of Reversible Logic Circuits | 255 |
雄 | 260 |
B | 263 |
Modeling of Power Consumption of Adiabatic Gates | 265 |
OUT | 268 |
An Adiabatic Multiplier | 276 |
Logarithmic Number System | 285 |
An Application of SelfTimed Circuits to the Reduction | 295 |
PARCOURS Substrate Crosstalk Analysis | 306 |
X | 310 |
EP CE ISO EPI CE | 311 |
Influence of Clocking Strategies on the Design of Low | 316 |
B | 320 |
500 | 323 |
Computer Aided Generation of Analytic Models | 327 |
מהדורות אחרות - הצג הכל
מונחים וביטויים נפוצים
adder algorithm applications approach architecture array ASIC block Boolean buffer cache capacitance cells chip circuit clock CMOS compiler complex components configuration coprocessor CPLD datapath delay developed device dynamically reconfigurable encoding energy environment evaluation execution Field Programmable FIFO Figure filter floorplanning FPGA full adder function gate glitches hardware IEEE implementation input interconnection interface KressArray latch logic logic gates Logic Synthesis loop macro mapping memory method microprocessor module multiplexer multiplier netlist operation optimizations output parallel parameters partition performance pipeline place and route power consumption power dissipation power estimation problem Proc processor prototype rDPU reconfigurable computing reduce registers RISC routing run-time sequence signal simulation SRAM structure switching synchronous synthesis Table techniques transistors values variables vectors VHDL VLIW VLSI voltage Xilinx Xputer