Embedded Computer Systems: Architectures, Modeling, and Simulation: 5th International Workshop, SAMOS 2005, Samos, Greece, July 18-20, ProceedingsTimo D. Hämäläinen Springer Science & Business Media, 4 ביולי 2005 - 476 עמודים The SAMOS workshop is an international gathering of highly quali?ed researchers from academia and industry, sharing in a 3-day lively discussion on the quiet and - spiring northern mountainside of the Mediterranean island of Samos. As a tradition, the workshop features workshop presentations in the morning, while after lunch all kinds of informal discussions and nut-cracking gatherings take place. The workshop is unique in the sense that not only solved research problems are presented and discussed but also (partly) unsolved problems and in-depth topical reviews can be unleashed in the sci- ti?c arena. Consequently, the workshop provides the participants with an environment where collaboration rather than competition is fostered. The earlier workshops, SAMOS I–IV (2001–2004), were composed only of invited presentations. Due to increasing expressions of interest in the workshop, the Program Committee of SAMOS V decided to open the workshop for all submissions. As a result the SAMOS workshop gained an immediate popularity; a total of 114 submitted papers were received for evaluation. The papers came from 24 countries and regions: Austria (1), Belgium (2), Brazil (5), Canada (4), China (12), Cyprus (2), Czech Republic (1), Finland (15), France (6), Germany (8), Greece (5), Hong Kong (2), India (2), Iran (1), Korea (24), The Netherlands (7), Pakistan (1), Poland (2), Spain (2), Sweden (2), T- wan (1), Turkey (2), UK (2), and USA (5). We are grateful to all of the authors who submitted papers to the workshop. |
תוכן
Keynote | 1 |
Reconfigurable Multiple Operation Array | 22 |
Design Space Exploration | 41 |
TwoDimensional Fast Cosine Transform for VectorSTA Architectures | 62 |
Towards Language Support for Reconfigurable Packet Processing | 82 |
Processor Architectures Design and Simulation | 93 |
A Novel JAVA Processor for Embedded Devices | 112 |
Tuning a Protocol Processor Architecture Towards DSP Operations | 132 |
Fast RealTime Job Selection with Resource Constraints Under Earliest | 242 |
Automatic ADLBased Assembler Generation for ASIP Programming Support | 262 |
A Hardware Accelerator for Controlling Access to MultipleUnit Resources | 279 |
RealTime Stereo Vision on a Reconfigurable System | 299 |
Compressed Swapping for NAND Flash Memory Based Embedded Systems | 314 |
A Scalable Embedded JPEG2000 Architecture | 334 |
Benchmarking Mesh and Hierarchical Bus Networks in SystemonChip | 354 |
System Level Design Modeling and Simulation | 374 |
CORDICAugmented Sandbridge Processor for Channel Equalization | 152 |
Exploiting Intrafunction Correlation with the Global History Stack | 172 |
Microarchitecture Performance Estimation by Formula | 192 |
Hardware Cost Estimation for ApplicationSpecific Processor Design | 212 |
Ultra Fast CycleAccurate Compiled Emulation of Inorder Pipelined | 222 |
Design and Implementation of a WLAN Terminal Using UML 2 0 Based | 404 |
DVBDSNG Modem High Level Synthesis in an Optimized Latency | 424 |
Moving Up to the Modeling Level for the Transformation of Data Structures | 445 |
Mixed VirtualReal Prototypes for Incremental System Design A Proof | 465 |
מהדורות אחרות - הצג הכל
מונחים וביטויים נפוצים
abstraction accelerator addition algorithm allows application approach architecture array basic block branch cache clock communication compared compiler complex components compression Computer configuration considered consumption cores cost cycle defined delay dependent described developed dynamic efficient embedded energy estimation evaluation example execution exploration Figure first FPGA function hardware IEEE implementation improve increase input instruction language latency logic mapping matching memory method multiple needed node object obtained operations optimization output packet parallel parameters partitioning pattern performance phase pipeline platform prediction presented priority processing processor proposed protocol real-time reconfigurable reduce reference represents resource routing scheduling selection shown shows signal simulation single space specific step stream structure Table task techniques tion transformations unit vector