Asynchronous Circuit DesignJohn Wiley & Sons, 5 באפר׳ 2004 - 424 עמודים With asynchronous circuit design becoming a powerful tool in the development of new digital systems, circuit designers are expected to have asynchronous design skills and be able to leverage them to reduce power consumption and increase system speed. This book walks readers through all of the different methodologies of asynchronous circuit design, emphasizing practical techniques and real-world applications instead of theoretical simulation. The only guide of its kind, it also features an ftp site complete with support materials. Market: Electrical Engineers, Computer Scientists, Device Designers, and Developers in industry. |
תוכן
| 1 | |
2 Communication Channels | 23 |
3 Communication Protocols | 57 |
4 Graphical Representations | 85 |
5 Huffman Circuits | 131 |
6 Muller Circuits | 207 |
7 Timed Circuits | 259 |
8 Verification | 295 |
9 Applications | 321 |
VHDL Packages | 347 |
Sets and Relations | 359 |
References | 365 |
| 393 | |
מהדורות אחרות - הצג הכל
מונחים וביטויים נפוצים
ack_patron ack_wine ack_wine+ AFSM algorithm assignment asynchronous circuits asynchronous design behavior block Boolean bottle of wine C-element Call Patron channel;signal clock Computer-Aided Design Consider constraint matrix context signal covering problem decode defined delay delay-insensitive digraph downto end process Example excitation region find fire firing first flow table function gate graph hazard hazard-free Huffman IEEE Transactions implementation init_ channel initial inout channel input burst insertion point integer intersects Karnaugh map Logic Synthesis loop lower bound minterms opcode output pair Petri nets POSET prime compatibles prime implicants privileged cube Proc procedure process begin produce protocol recanonicalize req_patron req_wine req_wine+ reset result satisfied self-timed sequential shelf shown in Figure signal transition specification speed-independent subcube synthesis temporal logic Theorem timer trace structure Transactions on Computers transition cube variable verification VHDL violating VLSI wait for delay(5,10 Wine Arrives winery wires XBM machine zone