Concurrent Hardware: The Theory and Practice of Self-timed DesignWiley, 8 בדצמ׳ 1993 - 388 עמודים Examines the theory and design of self-timed systems. The logical design of self-timed circuits (STCs) provides a focal point for, on the one hand, those interested in formal models of parallel computation and, on the other, hardware designers. The approach taken by the authors is to address general issues concerning the very nature of concurrency, as well as to demonstrate the particular features of asynchronous design. The book presents formal models of the specification and verification of parallel processes and describes methods for self-timed circuit synthesis and analysis. It is augmented by a demonstration-version of a CAD system called FORCAGE which consists of subsystems of behavior verification, self-timed circuit analysis and synthesis. The system can be run on a PC. |
תוכן
Models for a Specification of Parallel Processes | 1 |
The FORCAGE System and Selftimed Circuit Design | 9 |
Verification of Parallel System Behavior | 35 |
זכויות יוצרים | |
10 קטעים אחרים שאינם מוצגים
מונחים וביטויים נפוצים
a₁ AC₁ acyclic CD additional variables adjacency list algorithm analysis AND-composition asynchronous asynchronous circuits b₁ basic behavioral specification Boolean Boolean equations Boolean functions C-element C-State CD D1 cell Chapter circuit behavior complexity components contains contradictions contradictory correct CD corresponding TD cumulative cyclic CD cyclic code D₁ D1 and D2 Definition delay delay-insensitive detonant encoding equations equivalence relation equivalent ER(a ER(b event-based models example excitation region exists feasible sequence FIFO flip-flop FORCAGE formal functions gate gate delays hence i-th immediate predecessors implementation initial input instantiations logic methods modules non-repeated obtained occur operation original CD output parallel Petri nets phase problem Property Proposition reachable result RS-flip-flop RS-implementation s₁ segment self-timed circuits semantics semi-modular circuit set of changes shown in Figure signal graph source specification stuck-at faults subsystem switching synthesis tier transition two-phase unfolding verification vertices VLSI