Concurrent Hardware: The Theory and Practice of Self-timed DesignWiley, 8 בדצמ׳ 1993 - 388 עמודים Examines the theory and design of self-timed systems. The logical design of self-timed circuits (STCs) provides a focal point for, on the one hand, those interested in formal models of parallel computation and, on the other, hardware designers. The approach taken by the authors is to address general issues concerning the very nature of concurrency, as well as to demonstrate the particular features of asynchronous design. The book presents formal models of the specification and verification of parallel processes and describes methods for self-timed circuit synthesis and analysis. It is augmented by a demonstration-version of a CAD system called FORCAGE which consists of subsystems of behavior verification, self-timed circuit analysis and synthesis. The system can be run on a PC. |
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תוכן
Models for a Specification of Parallel Processes | 1 |
Verification of Parallel System Behavior | 35 |
Relationship Between the State and Eventbased Models | 59 |
זכויות יוצרים | |
9 קטעים אחרים שאינם מוצגים
מונחים וביטויים נפוצים
acyclic CD additional variables adjacency list algorithm analysis AND-composition asynchronous asynchronous circuits basic behavioral specification Boolean equations Boolean functions C-element C-State cell Chapter circuit behavior complexity components construct contains contradictions contradictory correct CD corresponding TD cumulative cyclic CD cyclic code Definition delay-insensitive detonant disengageable arcs elements encoding equivalence relation equivalent ER(a ER(b event-based models example excitation region exists feasible sequence FIFO flip-flop FORCAGE formal functions gate gate delays hence immediate predecessors implementation initial input instantiations logic methods modules non-repeated obtained occur operation original CD output parallel periods Petri nets phase pipeline problem Property Proposition reachable representation result RS-flip-flop RS-implementation segment self-timed circuits semantics semi-modular circuit set of changes shown in Figure signal graph source specification strong precedence relation structure stuck-at faults sub-circuit subsystem switching synthesis theory tier two-phase unfolding verification vertices violation VLSI well-formed CD